In executing a program, a CPU executes the program while generating tasks (a task is an executable unit of CPU) from the program and scheduling the tasks. In the case of processing which requires assurance of an execution time, a scheduler can determine a priority of each task and a dispatcher can allocate each task to the CPU depending on the priority.
In a computer in which a plurality of CPU cores are mounted, the computer improves its processing efficiency by allocating a plurality of tasks to each CPU core while allowing temporal overlap (see Patent Document 1 for example). The Patent Document 1 describes a multi processor system configured to calculate degree of parallel processing capability for each task and allocate each task to each CPU core depending on the degree of parallel processing capability and length of processing time.
There is also a system configured to instruct a plurality of CPU cores to work on another OS so that each OS shares and executes tasks (see Patent Document 2 for example). The Patent Document 2 describes a multi processor system which controls processing loads among OSs by determining a load for each OS and instructing a CPU core working on an OS with a low processing load to work on an OS with a high processing load.
However, allocating tasks dynamically as in the CPU core described in Patent Document 2 may bring disadvantages. For example, in a series of processing of motor control, a task is often executed by applying an execution result of a previous task to a feedback control for a next task. For example, since it is difficult to rapidly increase a rotating speed of an electric motor, a task which determines an amount of current supplied to the electric motor based on the feedback control calculates the amount of current supplied to the electric motor so that it can obtain a target value depending on the previous amount of current.
In this way, sometimes a multi core system in a control system can not obtain a desired execution result if it can not utilize the execution result of the previous task. There is also a possibility that the system goes out of control due to sudden change in a controlled variable if it switches a CPU core to which a task is allocated simply depending on a processing load or it requests another CPU core to execute parallel processing.
In general, although a multi CPU core can transfer an execution result via a shared memory, IPC (Inter Process Communication), or the like, considering that contents in the shared memory may be destroyed or IPC may be delayed, relying only on such a structure is not enough.
Load distribution in such a multi core system is known in the prior art for a task of information-processing system. However, a data input corresponds one-to-one with a data output in the task of information-processing system and it is rare that an execution result of a previous task is required for a next task. Thus, it has not been proposed to allocate a task of information-processing system considering an execution result of a previous task so far.    [Patent Document 1] Japanese Patent Publication No. H10-143380    [Patent Document 2] Japanese Patent Publication No. 2007-188212